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### » DVM Test Report: LL_Nominal|F_Low|Disabled|100% Load|BodePlot

Test Details |
Schematic | DVM -- PFC_CCM_sync_DLL.sxsch
Test | LL_Nominal|F_Low|Disabled|100% Load|BodePlot
Date / Time | 22/03/2022 07:01
Report Directory | DVM_REPORTS\2022-03-22-06_18\LL_Nominal\F_Low\Disabled\100% Load\BodePlot
Log File | report.txt
Screenshot | schematic.png
Status | PASS
Simulator | simplis
Deck | input.deck
Init | input.deck.init
Measured Scalar Values |
Efficiency | 96.690688%
gain_crossover_freq | 10.148314
gain_margin | 28.991123
ILOAD | AVG 250.05778m MIN 248.6188m MAX 251.5123m RMS 250.05982m PK2PK 2.8934974m
ISRC | AVG -294.47158p MIN -1.2397832 MAX 1.2397832 RMS 861.02898m PK2PK 2.4795665
min_phase | 17.346815
min_phase_freq | 63.472646
phase_crossover_freq | 87.324127
phase_margin | 58.866314
Power(LOAD) | 100.04786
Power(SRC) | 103.47208
VLOAD | AVG 400.09244 MIN 397.79008 MAX 402.41968 RMS 400.09572 PK2PK 4.6295958
VSRC | AVG -275.91442p MIN -169.99978 MAX 169.99978 RMS 120.208 PK2PK 339.99957
Measured Spec Values |
Max_VLOAD | PASS: Max. Output1 Voltage (402.42) is less than or equal to Max. Output1 Voltage Spec (420)
Min_VLOAD | PASS: Min. Output1 Voltage (397.79) is greater than or equal to Min. Output1 Voltage Spec (380)
min_gain_margin | PASS: Gain Margin (28.9911) is greater than Min. Gain Margin (12)
min_phase_margin | PASS: Phase Margin (58.8663) is greater than Min. Phase Margin (35)
Bode Plot GAIN PHASE
SXGPH File | simplis_ac55_4438.sxgph
LOAD VLOAD ILOAD
SXGPH File | simplis_pop8_4350.sxgph
SRC VSRC ISRC
SXGPH File | simplis_pop8_4339.sxgph
Other SXGPH Files |
Output#pop | simplis_pop8_4237.sxgph
Vdc-Vdrain#pop | simplis_pop8_4248.sxgph
SIGNAL#pop | simplis_pop8_4264.sxgph
Samples#pop | simplis_pop8_4275.sxgph
COMP#pop | simplis_pop8_4296.sxgph
triggers#pop | simplis_pop8_4317.sxgph
VL#pop | simplis_pop8_4328.sxgph
Load_offset#pop | simplis_pop8_4382.sxgph