* SCHEMATIC : ..\..\LTC3406B - DVM ADVANCED.sxsch
* TESTPLAN : dvm_advanced.testplan
* ORIGINALTP: dvm_builtin-syncbuck_1in_1out.testplan
* DATE : 2015-12-10
* TIME : 5:38 PM
* REPORT DIR: D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM
* NUM TESTS : 6
* HTMLTITLE : SIMPLIS DVM Test Report Overview
*
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|Light Load
* PROGRESS : 1 of 6
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM\Ac Analysis\Bode Plot\Vin Nominal\Light Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\Light Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : FAIL
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 11 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|50% Load
* PROGRESS : 2 of 6
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM\Ac Analysis\Bode Plot\Vin Nominal\50% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\50% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Ac Analysis|Bode Plot|Vin Nominal|100% Load
* PROGRESS : 3 of 6
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM\Ac Analysis\Bode Plot\Vin Nominal\100% Load/report.txt
* DECK : Ac Analysis\Bode Plot\Vin Nominal\100% Load\input.deck
* INIT : Ac Analysis\Bode Plot\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Ac Analysis\Bode Plot\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 10 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|Light Load
* PROGRESS : 4 of 6
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM\Steady-State\Steady-State\Vin Nominal\Light Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\Light Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\Light Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\Light Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|50% Load
* PROGRESS : 5 of 6
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM\Steady-State\Steady-State\Vin Nominal\50% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\50% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\50% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\50% Load\report.txt.html
* TEST TIME : 8 seconds
*
* TEST : Steady-State|Steady-State|Vin Nominal|100% Load
* PROGRESS : 6 of 6
* SIMULATOR : simplis
* EXECUTED : SIMPLIS
* LOG : D:\documentation.simplistechnologies.com\branches\build80_xml\library\examples\dvm_tutorial\LTC3406B\DVM_REPORTS\2015-12-10-5_38_PM\Steady-State\Steady-State\Vin Nominal\100% Load/report.txt
* DECK : Steady-State\Steady-State\Vin Nominal\100% Load\input.deck
* INIT : Steady-State\Steady-State\Vin Nominal\100% Load\input.deck.init
* STATUS : RUN
* RSTATUS : PASS
* REPORT : Steady-State\Steady-State\Vin Nominal\100% Load\report.txt.html
* TEST TIME : 8 seconds
*
*
* TOTAL TIME: 58 seconds
* TESTS RUN : 6 of 6